module aib_pair_behav #(
    parameter MW=160
)(
    input clk,
    input rst,
    input [MW-1:0] l_data_in_f,
    output reg [MW-1:0] l_data_out_f,
    input [MW-1:0] r_data_in_f,
    output reg [MW-1:0] r_data_out_f
);
    reg [MW-1:0] rl_data;
    reg [MW-1:0] lr_data;
    always @(posedge clk) begin
        if(rst) begin
            l_data_out_f<=0;
            r_data_out_f<=0;
            lr_data<=0;
            rl_data<=0;
        end else begin
            rl_data<=r_data_in_f;
            l_data_out_f<=rl_data;
            lr_data<=l_data_in_f;
            r_data_out_f<=lr_data;
        end
    end
endmodule

